Status Byte and Event Registers

The instrument includes a number of standard registers: the "Standard Event Status Register", "Status Byte Register", "Event Status Register 0".

The status byte

Each bit of the status byte is a summary (logical OR) of the event register corresponding to that bit.

Status byte | Contents
bit 7 | Unused: 0
bit 6 | Unused: 0
bit 5 (ESB) | Event summary bit. Shows a summary of the Standard Event Status Register.
bit 4 (MAV) | Message available Shows that a message is present in the output queue.
bit 3 | Unused: 0
bit 2 | Unused: 0
bit 1 | Unused: 0
bit 0 (ESB0) | Event summary bit 0 Shows a summary of Event Status Register 0.

The following command read the status byte.

Read the status byte | *STB?

Standard Event Status Register (SESR)

Bit 5 of the status byte indicates the summary of this register.
The following events clear the contents of the Standard Event Status Register:

1. When the *CLS command is received.

2. When the contents have been read by an *ESR? query.

3. When power is turned off and on again.

Standard Event Status Register (SESR) | Contents
bit 7 (PON) | Power has been turned on again. Since this register was last read, the instrument has been powered off and on. Initialized to one at power on.
bit 6 (URQ) | User request: not used.
bit 5 (CME) | Command error. There is an error in a command that has been received: either an error in syntax, or an error in meaning.
bit 4 (EXE) | Execution error. An error has occurred while executing a command. Range or Mode error.
bit 3 (DDE) | Device-dependent error. A command could not be executed due to an error other than a command error, query error or an execution error.
bit 2 (QYE) | Query error. The queue is empty, or data loss has occurred (queue overflow).
bit 1 (RQC) | Request for controller rights (not used) Unused: 0
bit 0 (OPC) | Operation finished. Only set for the *OPC command.

The following commands are used to read the Standard Event Status Register.

Read the Standard Event Status Register | *ESR?

Event Status Register 0 (ESR0)

The summary of this register is set in bit 0 of the status byte.
The following events clear the contents of Event Status Register 0:

1. When the *CLS command is received.

2. When the contents have been read by an :ESR0? query.

3. When power is turned off and on again.

Event Status Register 0 (SESR0) | Contents
bit 7 | Unused: 0.
bit 6 | Unused: 0.
bit 5 | Unused: 0.
bit 4 | Unused: 0.
bit 3 | Unused: 0.
bit 2 | Trigger wait finished (set when a trigger event occurs).
bit 1 | Measurement operation concluded (set by STOP).
bit 0 | Error not related to interface.

The following commands read the Event Status Register 0.

Read Event Status Register 0 | :ESR0?